The escalating demands for high densification and performance associated with ultra large scale integration semiconductor devices require design features of 0.25 microns and under, such as 0.18 microns, increased transistor and circuit speeds, high reliability and increased manufacturing throughput. The reduction of design features to 0.25 microns and under challenges the limitations of conventional interconnection technology, including conventional photolithographic, etching and deposition techniques.
Conventional methodology for forming patterned metal layers comprises a subtractive etching or etch back step as the primary metal patterning technique. Such a method involves the formation of a first dielectric layer on a semiconductor substrate, typically monocrystalline silicon, with conductive contacts formed therein for electrical connection with an active region on the semiconductor substrate, such as a source/drain region. A metal layer, such as aluminum or an aluminum alloy, is deposited on the first dielectric layer, and a photoresist mask is formed on the metal layer having a pattern corresponding to a desired conductive pattern. The metal layer is then etched through the photoresist mask to form the conductive pattern comprising metal features separated by gaps, such as a plurality of metal lines with interwiring spacings therebetween. A dielectric layer is then applied to the resulting conductive pattern to fill in the gaps and the surface is planarized, as by conventional etching or chemical-mechanical polishing (CMP) planarization techniques.
As shown in FIGS. 1 and 2, conventional practices comprise depositing metal layer 11 on dielectric layer 10 which is typically formed on a semiconductor substrate containing an active region with transistors (not shown). After photolithography, etching is then conducted to form a patterned metal layer comprising metal features 11a, 11b, 11c and 11d with gaps therebetween. A dielectric material 12, such as spin on glass (SOG), is typically deposited to fill in the gaps between the metal features, and baked at a temperature of about 300.degree. C. to about 450.degree. C., for a period of time up to about two hours, depending upon the particular SOG material employed, to enhance the dielectric properties of SOG. A layer of silicon dioxide is deposited by plasma enhanced chemical vapor deposition (PECVD) to cap the SOG layer and is subsequently planarized, as by CMP, before the next level of via and metal wiring is attempted.
As feature sizes, e.g., metal lines and interwiring spacings, shrink to 0.25 microns and below, such as 0.18 microns, it becomes increasingly difficult to satisfactorily fill in the interwiring spacings voidlessly and obtain adequate step coverage. Hydrogen silsesquioxane (HSQ) offers many advantages for use in interconnect patterns. HSQ is relatively carbon free, thereby avoiding poison via problems. Moreover, the absence of carbon renders it unnecessary to etch back HSQ below the upper surface of the metal lines to avoid shorting. In addition; HSQ exhibits excellent planarity and is capable of gap filling interwiring spacings less than 0.15 microns employing conventional spin-on equipment. HSQ undergoes a melting phase at approximately 200.degree. C., but does not convert to the high dielectric constant glass phase until reaching temperatures of about 400.degree. C. for intermetal applications and about 700.degree. C. to about 800.degree. C. for premetal applications.
However, after experimental investigation and testing, it was found that the use of HSQ to gap fill the spaces between metal features results in a degradation of the electromigration resistance of the metal feature, e.g., a metal line. Electromigration failure is a serious limitation on the lifetime and reliability of conventional semiconductor devices and is attributed to the conductive interconnection lines. The phenomenon of electromigration involves the flow of electrons causing the migration of atoms, thereby generating voids and hillocks. The formation of voids creates an opening in a conductive interconnection line, thereby decreasing the performance of the interconnection line. The formation of voids generates areas of increased resistance which undesirably reduce the speed of a semiconductor device. Thus, the electromigration phenomenon constitutes a limitation on the lifetime of the conductive interconnection line, as well as the performance of the semiconductor device.
Electromigration in a metal interconnection line can be characterized by the movement of ions induced by a high electrical current density. As miniaturization of the feature size of the semiconductor device increases, the current density also increases and, hence, electromigration induced metallization failures increase. Current metallization failures resulting from electromigration exceed about 30% of the total of metallization failures.
The continuing demand for increased miniaturization requires conductive patterns comprising features, such as conductive lines with interwiring spacings therebetween, having a feature size of about 0.25 microns and under. Semiconductor devices comprising conductive patterns having sub-micron design features are characterized by a high electrical current density and, consequently, increased metallization and electromigration failures. The requirement for a longer electromigration lifetime is of critical importance for an interconnection system.
Prior attempts to restrain electromigration involve the use of overcoating, alloying, or multilevel metallization.
There exists a need for semiconductor technology enabling the use of HSQ as a gap fill layer without adversely affecting the electromigration resistance of metal features, such as metal lines. There exists a particular need for semiconductor technology enabling the use of HSQ as a gap fill layer for metal features of about 0.25 microns and under without adversely affecting electromigration resistance.